1. Field of the Invention
The present invention relates to an apparatus and a method for providing a protective cover plate for a packaged semiconductor chip. More particularly, the present invention relates to attaching a protective plate on a flip chip, wherein the protective plate may also serve as a heat sink.
2. State of the Art
Chip On Board ("COB") techniques are used to attach semiconductor dice to a printed circuit board, including flip chip attachment, wirebonding, and tape automated bonding ("TAB"). Flip chip attachment consists of attaching a flip chip to a printed circuit board or other substrate. A flip chip is a semiconductor chip that has a pattern or array of terminals spaced around an active surface of the flip chip for face down mounting of the flip chip to a substrate. Generally, the flip chip active surface has one of the following electrical connectors: Ball Grid Array ("BGA")--wherein an array of minute solder balls is disposed on the surface of a flip chip that attaches to the substrate ("the attachment surface"); Slightly Larger than Integrated Circuit Carrier ("SLICC")--which is similar to a BGA, but having a smaller solder ball pitch and diameter than a BGA; or a Pin Grid Array ("PGA")--wherein an array of small pins extends substantially perpendicularly from the attachment surface of a flip chip, such that the pins conform to a specific arrangement on a printed circuit board or other substrate for attachment thereto. With the BGA or SLICC, the solder or other conductive ball arrangement on the flip chip must be a mirror-image of the connecting bond pads on the printed circuit board so that precise connection is made. The flip chip is bonded to the printed circuit board by refluxing the solder balls. The solder balls may also be replaced with a conductive polymer. With the PGA, the pin arrangement of the flip chip must be a mirror-image of the pin recesses on the printed circuit board. After insertion, the flip chip is generally bonded by soldering the pins into place. A variation of the pin-in-recess PGA is a J-lead PGA, wherein the loops of the J's are soldered to pads on the surface of the circuit board.
Glob top and underfill materials are often used to hermetically seal the flip chips on the substrate. An underfill encapsulant is generally disposed between the semiconductor chip and the printed circuit board or substrate for environmental protection and to enhance the attachment of the semiconductor die to the substrate. In certain applications, only an underfill encapsulant is used in the semiconductor assembly without protecting the back surface of the semiconductor chip. The exposure of the semiconductor chip back surface leaves the semiconductor chip susceptible to damage. Furthermore, the application of the underfill encapsulant must be closely monitored. For example, too little underfill does not protect the device sufficiently enough from outside contamination and can give rise to a greater concentration of voids. Such voids can lead to the catastrophic failure of the chip. If too much underfill is used, the underfill encapsulant can rise to cover the edges of the chip, can expand or can spread out to adjacent areas of the board that do not require underfill.
Since the underfill encapsulant alone does not protect the back of the dice, an additional protection step of providing a glob top is typically used. As shown in FIG. 1, after assembly of a COB component 100, an underfill encapsulant 114 is generally placed between a semiconductor chip or flip chip 104 that is attached to a substrate 106 via a plurality of electrical connections 108 that extend between a plurality of semiconductor chip bond pads 110 and a corresponding plurality of substrate bond pads 112. The technique for applying the underfill encapsulant comprises dispensing the underfill encapsulant in a liquid form and allowing capillary action to draw it between the semiconductor chip 104 and the substrate 106. The underfill encapsulant then solidifies upon oven curing and reinforces all electrical connections 108. A variety of polymers can be used as underfill encapsulants, including thermosetting molding compounds such as silicones, epoxies, polyamides, and parylenes. A glob of encapsulant material 102 (usually epoxy or silicone or a combination thereof) is generally applied to the COB assembly 100 to surround the semiconductor chip 104 and the substrate 106. Organic resins generally used in the glob top encapsulation are usually selected for low moisture permeability and low thermal coefficient of expansion to avoid exposure of the encapsulated chip to moisture or mechanical stress, respectively. However, even though the chemical properties of these glob top materials have desirable properties for encapsulation, the thermal and electrical properties are often not optimal for removing heat efficiently away from the semiconductor dice or for use in high temperature areas. Furthermore, the addition of glob materials can induce detrimental stresses that can cause catastrophic failures. The stresses occur when the glob top is cured and has different mechanical characteristics such as an expansion coefficient compared to the underfill material.
Other techniques for protecting semiconductor dice include U.S. Pat. No. 5,432,676 which teaches a lid placed over a cavity containing a plurality of semiconductor dice and U.S. Pat. No. 5,477,082 which teaches a heat sink or non-heat-conductive covering to form a top surface of a module.
Every semiconductor chip in a COB assembly generates heat during operation. Some glob tops and package encapsulation materials may serve to draw the heat away from most semiconductor chips. Indeed, one factor in choosing a package encapsulation material is its thermal dissipation properties. If the operating temperature of the semiconductor chip is not controlled or accommodated, reliability problems of the chip or system in which the chip is installed may occur due to excess temperature rise during operation. The device/semiconductor junction temperature (the location of the heat source due to power dissipation) must be maintained below a predetermined limiting value, typically such as 85.degree. C. The primary reason to control device/semiconductor junction temperature is that the performance of the device is a sensitive function of device temperature. In addition, various failure mechanisms are thermally activated, and failure rates become excessive above the desired temperature limit causing reliability concerns. Furthermore, it is important to control the variation in device operating temperature across all the devices in the system. This is also due to the temperature sensitivity of switching voltage, since too large a variation from device to device would increase the voltage range over which switching occurs, leading to switching errors due to noise and power-supply fluctuations. Moreover, the fluctuations in temperature cause differential thermal expansions that give rise to a fatigue process that can lead to cracks occurring in the COB assembly during burn-in or general operation.
Thus, high heat producing semiconductor dice, such as a microprocessor, may require adjustments in size of the COB assembly and will often require the addition of metal heat-dissipating fins, blocks, or the like on the package. Referring to drawing FIG. 2, a finned COB assembly 200 is illustrated. The finned COB assembly 200 comprises a semiconductor chip or flip chip 202 which is attached to a substrate 204 via a plurality of electrical connections 206 which extend between a plurality of semiconductor chip bond pads 208 and a corresponding plurality of substrate bond pads 210. An underfill encapsulant 212 is disposed between the semiconductor chip 202 and the substrate 204. A cap 214 having a plurality of heat-dissipating fins 216 is attached to an upper surface 218 of the semiconductor chip 202 with a layer of thermally conductive adhesive 220. U.S. Pat. No. 5,396,403 issued Mar. 7, 1995 to Patel illustrates a finned heat sink arrangement. The arrangement comprises a plurality of semiconductor chips attached to a thermally conductive plate with a thermally conductive paste. The thermally conductive plate is in turn connected to a finned heat sink with a thermally conductive paste. However, the addition of heat-dissipating fins or the like substantially increases the cost of production for COB assemblies.
Simpler heat dissipation methods have been attempted. U.S. Pat. No. 5,488,254 issued Jan. 30, 1996 to Nishimura et al. and U.S. Pat. No. 5,489,801 issued Feb. 6, 1996 to Blish relate to encasing a heat slug (a piece of heat conducting material) in the encapsulation material. Although each of these patents attempts to address the problems of potential differences in the thermal coefficient of expansion between the heat slug and the encapsulation material, these attempts are never entirely successful and the adhesion interfaces between the heat slug and the encapsulation material may become separated allowing moisture to reach and destroy the encased semiconductor chip.
Therefore, it would be advantageous to develop a technique and assembly for inexpensively forming a protection shield on a semiconductor chip in combination with commercially-available, widely-practiced semiconductor device fabrication techniques. It would also be advantageous if the protective shield also served as a heat dissipation mechanism, and also reduced expansion differences between the underfill and gob top material conventionally used for encapsulation.